1. Field of Invention
The present invention relates to a non-linear transient analysis module and method for a phase locked loop. More particularly, the present invention relates to a non-linear transient analysis module and its method that uses two calculation techniques on a cycle by cycle and piecewise linear basis for phase locked loop in the time domain.
2. Description of Related Art
Phase locked loop (PLL) circuits are widely used in wireless communication systems and control systems. The phase locked loop circuits are essential parts especially for frequency modulation and demodulation in System on Chip (SoC) integrated circuits.
In the early days, the PLL circuits were pure analog circuits. Since in those days there were no computer for simulation and calculation, circuit analyses was done by hand calculation. Any active circuits which consist of transistors or old vacuum tubes are essentially non-linear circuits. Thus signals need to be small enough so that the transistors and the vacuum tubes are operated in the linear regions.
Analog/Mixed-signal integrated circuits design is more and more complicated so the conventional simulation tools SPICE (Simulation Program with Integrated Circuit Emphasis), which is a program used in circuit description and simulation, or FastSPICE (Fast Simulation Program with Integrated Circuit Emphasis) do not satisfy the demands of SoC in simulation speed and design capacity.
EDA (Electronic Design Automation) enables digital simulators (ex. Verilog) and analog simulators (ex. SPICE) to be used simultaneously, and then develops a co-simulation environment for design and verification, which is so-called mixed-mode simulation, in order to improve the predicament.
Process of mixed-signal circuit design often encounters the problem of using Verilog and SPICE for co-simulation. A conventional method converts the results of the Verilog into the SPICE format, and then the simulator in the SPICE simulates the transistor-level circuit.
As a result the mixed-signal circuits design has become more complicated. There are two ways to improve the simulation speed and the design capacity of the analog circuit. One is to develop a more powerful analog simulator such as FastSPICE. The improvement is obvious when used in a repetitive circuit. The other is to design the analog behavior model of the analog circuit, but the analog behavior model varies. The parameter design of the analog circuit is not easy because simulation accuracy must be considered. The analog behavior model design is still a trend of circuit design in the feature.
The present invention uses the non-linear transient analysis method to process the piecewise linear calculation. The analysis needs only two calculations per cycle, takes only a few seconds and is very fast by comparison with an HSPICE simulation developed by MetaSoftware company where the HSPICE needs hundreds of thousands of calculations.